The invention relates to a code generator which simultaneously generates a plurality of code series which are in mutually orthogonal relationship to each other, and also a CDMA radio receiver using same.
A code series generator of the kind described is used for various purposes in the field of communication. For example, in order to preserve secrecy of information being transmitted in a radio communication, digital data from the transmitting side is multiplied by a code series, referred to as a secret code, in a scrambler circuit while received data is multiplied by a secret code which is of the same type and of the same phase as the secret code used on the transmitting side in a descrambler circuit of the receiving side. In the CDMA radio communication, a code series, called a spread code, is used to provide a multiple access. On the transmitting side, data is multiplied by a spread code before transmission while on the receiving side, a received signal is multiplied by the spread code to derive data. Different codes are orthogonal to each other, and a communication is enabled by the use of the spread code of the same type and of the same phase on both the transmitting and the receiving side.
If a code series used on the transmitting side is unknown in the secret code communication or CDMA radio communication, it is necessary on the receiving side to retrieve the type of the code series used on the transmitting side. Because the number of the types of the code series used is fixed, a plurality of code series may be used in parallel during the retrieval to reduce a length of time required for the retrieval. Also, in the CDMA radio communication, if a single user simultaneously uses a plurality of code series (multicode), a high rate of transmission is enabled, thus allowing a variety of services to be offered.
FIG. 1A shows an example of an arrangement for a receiver of a mobile unit in a conventional CDMA radio communication. Describing a flow of a received signal in this arrangement, a signal received at an antenna 11 is demodulated in a radio unit 12 to be converted into a baseband signal, which is then converted into a digital signal in an A/D converter 13. Supplied to code generators 141-144 are spread code information which is detected by a multi-path searcher 15 as well as a frame timing. This allows the code generators 141-144 to generate a code each which is synchronized with a spread code used on the transmitting side. A multiplication between the baseband signal from the A/D converter 13 and the spread codes from the code generators 141-144 then takes place in correlators 161-164 to effect a despreading, thus recovering an original signal. Subsequently, the reversely spread signals are detected in detectors 171-174 and are then synthesized by a RAKE receiver 18 to be delivered to a signal processing unit 19. The despreading process which takes place in the correlators 161-164 permits a separation of signals from different transmission paths (or multi-path) which are contained in the received signal, and thus this reception processing represents a RAKE reception with path diversity effect.
Gold code series, for example, which exhibit an excellent orthogonality between codes is used for the code series mentioned. Gold code series generator comprises a first M-series generator 14A, a second M-series generator 14B, and an exclusive OR 14X which calculates an exclusive OR of both outputs from the M-series generators 14A, 14B, as shown in FIG. 2A. It is to be understood that throughout subsequent Figures, the symbol including xe2x80x9c+xe2x80x9d mark in a circle indicates an exclusive OR. The first and the second M-series generator 14A, 14B generates mutually different M-series, that is, codes which are distinct from each other if they are compared against each other at any phase relationship.
M-series generator 14A comprises a shift register, SR and an exclusive OR XR, and a value in each shift stage is shifted by one stage toward a last stage S5 in response to each shift clock, whereby M-series is delivered as an output from the last stage S5 of the shift register SR. Simultaneously, the exclusive OR XR forms an exclusive OR of the output from the last stage and an output from an intermediate shift stage, with its output being fed back to an initial stage S1 of the shift register SR. In the second M-series generator 14B, each of a plurality of shift stages of its shift register is connected with an exclusive OR XR to form an exclusive OR with an output to be fed back to the initial stage. Thus, mutually different M-series are generated by changing the locations and/or the number of shift stages which are connected with the exclusive OR""s. A register value in a single shift register which defines M-series changes for every clock, but retains a periodicity such that it returns to its original initial value after the register value has gone a round through all possible combinations. Denoting the number of shift stages of the shift register SR by n, the length of the period is equal to 2nxe2x88x921 chips. By adding together (or forming an exclusive OR of) two such different M-series in the exclusive OR 14X, there is obtained Gold code series having the same period as the M-series.
Different Gold code series can be formed by changing an initial value loaded into a shift register which defines M-series. A user can use a plurality of different Gold code series simultaneously to achieve a reduction in the length of time required to identify Gold code series used on the transmitting side or a high rate data transmission.
It has been customary in the art of radio communication to use a separate code generator for each code series in order to generate a plurality of different code series simultaneously. Accordingly, as the number of code series generated increases, there results an increase in both circuit scale and power dissipation.
Japanese Laid-Open Patent Application No. 264,098/1995 discloses a spread spectrum communication system including a code generator for simultaneously generating a plurality of spread codes and which is constructed as shown in FIG. 2B. Specifically, an output from an M-series generator 14 is supplied to an end bit adding unit 14C0 and to a shift register 14SR, an output from each shift stage of which is supplied to an end bit adding unit 14C1-14Cn, respectively, the end bit adding units delivering a series of codes which are substantially orthogonal to each other. The M-series generator 14, the shift register 14SR and the end bit adding units 14C0-14Cn are operated by a same clock. In this manner, (n+1) spread codes are generated.
With the code generator shown in FIG. 2B, the circuit scale and the power dissipation are both reduced than when a code generator is used for each code series.
In the code generator shown in FIG. 2B, the mutual orthogonality is given as a result of adding one bit to the end of each input code series or to the end of a code series having a sequential phase offset by one bit (or to the end of each code period) in each of the end bit adding units 14C0-14Cn. However, a phase offset by one bit produces a significant cross-correlation between the codes. Assume that output codes delivered from the end bit adding units 14C0, 14C1 are code 1 and code 2 (xe2x80x9c1xe2x80x9d being added to the end of code 1 and code 2) as shown in FIG. 2C, for example. If one bit shift to the right is caused as by a transmission path delay to the code 1, there would be only two bit differences for the leading bit and the trailing bit between the code 1 which is shifted by one bit to the right and the code 2, producing a remarkable magnitude of cross-correlation between the codes, which can no longer be treated as distinct codes.
Thus, a plurality of codes generated by a code generator as shown in FIG. 2B involves a likelihood of causing an interchannel interference when they are used in a communication such as a mobile communication which is subject to a varying propagation delay.
As mentioned previously, the code series generated by the M-series generator has a length of period which is equal to 2nxe2x88x921 chips. When code series are taken from each shift stage of the shift register SR of the M-series generator 14A, there are obtained code series which have different amounts of delay. The code series obtained in this manner are equal to n in number as may be derived from the respective stages of the shift register SR, even though there are (2nxe2x88x921) delays for the code series inasmuch as the length of period is equal to 2nxe2x88x921 chips. It is also to be noted that they are merely distinguished by a sequential phase offset by one chip. Arbitrary code series which are sufficiently spaced apart in phase may be chosen from (2nxe2x88x921) code series, for example, by connecting (2nxe2x88x921) bit shift register to the output of the M-series code generator 14A and taking code series from arbitrary shift stages of this shift register. However, (2nxe2x88x921) bit shift register needs an increased circuit scale. Alternatively, code generators would have to be used which generate code series having desired delays between them. This again needs an increased circuit scale if the number of code series increases.
Accordingly, it is a first object of the invention to provide a simultaneous plural code series generator capable of providing a plurality of code series having desired delays between them with a reduced circuit scale.
It is a second object of the invention to provide a code generator which simultaneously generates a plurality of codes with a reduced circuit scale and with a reduced power dissipation while maintaining a reduced cross-correlation between the codes in the event of occurrence of a phase offset between the codes, thus maintaining the orthogonality.
It is a third object of the invention to provide a CDMA receiver incorporating the plural code series generator and capable of performing a cell search and/or multi-path search in a reduced interval of time.
According to a first aspect of the invention, at least one code series is generated which is delayed with respect to code series generated by code generating means, and an exclusive OR of the undelayed and the delayed code series is formed to provide code series which obtains a desired delay. A plurality of means for delivering code series having a desired delay through the exclusive OR are provided.
According to a second aspect of the invention, the simultaneous plural code series generator according to the first aspect is provided, and second code series generating means is also provided which generate code series which is substantially orthogonal to code series generated by code series generating means within the simultaneous plural code series generator, an exclusive OR between the code series from the second code series generating means and each of the plurality of code series from the simultaneous plural code series generator being formed to provide a plurality of code series simultaneously which are substantially orthogonal to each other.
According to a third aspect of the invention, a plurality of arbitrary spread codes are simultaneously generated by single means, and a multiplication is effected for an arbitrary combination of the spread codes and a received signal to derive a correlation value, which is used to perform a search for a visitor cell or a border cell.
The single spread code generating means generates a plurality of code series, each of which is imparted an equal delay, and an exclusive OR of these having the equal delay is formed, thereby simultaneously generating spread codes of different codes.